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Integrated Circuit Systems, Inc.
AV9173-01
Video Genlock PLL
General Description
The AV9173-01 provides the analog circuit blocks required for implementing a video genlock dot (pixel) clock generator. It contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). By grouping these critical analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost. When used with an external clock divider, the AV9173-01 forms a Phase-Locked Loop configured as a frequency synthesizer. The AV9173-01 is designed to accept video horizontal synchronization (h-sync) pulses and produce a video dot clock. A separated, negative-going sync input reference pulse is required at pin 2 (I N). The AV9173-01 is also suited for other clock recovery applications in such areas as data communications.
Features
* * * * * * * * * Phase-detector/VCO circuit block Ideal for genlock system Reference clock range 25 kHz to 1 MHz for full output clock range Input clocks down to 12 kHz possible with restricted output conditions (see Table 1) Output clock range 1.25 to 75MHz On-chip loop filter Single 5 volt power supply Low power CMOS technology Small 8-pin DIP or SOIC package
Block Diagram
AV9173-01RevC052197P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
AV9173-01
Pin Configuration
8-Pin DIP or SOIC
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME FBIN IN GND FS0 OE CLK1 VDD CLK2 TYPE Input Input -- Input Input Output -- Output DESCRIPTION Feedback Input Input for reference sync pulse Ground Frequency Select 0 input Output Enable Clock Output 1 Power Supply (+5V) Clock Output 2 (Divided-by-2 from Clock 1)
Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)
fIN (kHz) 12 fIN 14 kHz 14 < fIN 17 kHz 17 < fIN 30 kHz 30 < fIN 35 kHz 35 < fIN 1000 kHz fOUT for FS = 0 (MHz) CLK1 Output CLK2 Output 44.0 to 75 22.0 to 37.5 30.0 to 75 15.0 to 37.5 25.0 to 75 12.5 to 37.5 7.5 to 37.5 15.0 to 75 5.0 to 37.5 10.0 to 75 fOUT for FS = 1 (MHz) CLK1 Output CLK2 Output 11.0 to 18.75 5.5 to 9.375 7.5 to 18.75 3.75 to 9.375 6.25 to 18.75 3.125 to 9.375 3.75 to 18.75 1.875 to 9.375 2.5 to 18.75 1.25 to 9.375
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AV9173-01
Using the AV9173-01
Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video "genlock" (generator lock) circuit is required. The AV9173-01 integrates the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the AV9173-01 is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (h-sync) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. The clock feedback divider shown in Figure 1 is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: AC specifications (VCO frequency), an input as low as 12kHz (such as NTSC or PAL h-sync) can be used. The output hook-up of the AV9173-01 is dictated by the desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration.
FS0 State 0 0 1 1
Output Used CLK1 CLK2 CLK1 CLK2
Frequency Range 10 - 75 MHz 5 - 37.5 MHz 2.5 - 18.75 MHz 1.25 - 9.375 MHz
Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). For further discussion of VCO/PLL operation as it applies to the AV9173-01, please refer to the AV9170 application note. The AV9170 is a similar device with fixed feedback dividers for skew control applications.
fOUT = f IN * N where N is external divide ratio
Both AV9173-01 input pins IN and FBIN respond only to negative-going clock edges of the input signal. The h-sync signal must be constant frequency in the 25 kHz to 1 MHz range and stable (low clock jitter) for creation of a stable output clock. Refer to Application Brief (AB01) for additional details on use of input frequencies below 25kHz. By following the guidelines in this brief and meeting the test conditions in the
Figure 1: Typical Application of AV9173-01 in a Video Genlock System
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AV9173-01
Absolute Maximum Ratings
VDD (referenced to GND) . . . . . . . . . . . . . . . . 7.0 V Operating Temperature under Bias . . . . . . . . . 0 C to +70 C Storage Temperature . . . . . . . . . . . . . . . . . . . . - 65C to +150C Voltage on I/O pins referenced to GND . . . . . GND - 0.5 V to VDD + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 0.5 watts
Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristic
VDD = +5V 5%, TA = 0C to 70C, unless otherwise stated
DC CHARACTERISTICS
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 Output High Voltage1 Output High Voltage1 Output High Voltage1 Supply Current Notes:
SYMBOL VIL VIH IIL IIH VOL VOH1 VOH2 VOH3 IDD
TEST CONDITIONS MIN VDD = 5V -- VDD = 5V 2.0 VIN = 0V -5 VIN = VDD -5 IOL = 8mA -- IOH = -1mA, VDD -0.4V VDD = 5.0V IOH = -4mA, VDD -0.8V VDD = 5.0V IOH = -8mA 2.4 Unloaded, 50 MHZ --
TYP -- -- -- -- -- -- -- -- 20
MAX 0.8 -- -- 5 0.4 -- -- -- 50
UNITS V V A A V V V V mA
1. Duty cycle measured at 1.4V. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4.
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AV9173-01
Electrical Characteristics
VDD = +5V 5%, TA = 0C to 70C, unless otherwise stated
AC CHARACTERISTICS
SYMBOL TEST CONDITIONS r ICLK ICLK f tr1 15pF load; 0.8 to 2.0V 15pF load; 1 Output Rise time tr2 20% to 80% VDD tf1 15pF load; 2.0 to 0.8V Output Fall time1 15pF load; 1 Output Fall time tf2 80% to 20% VDD dt 15pF load Output Duty Cycle1 T1s1 CLK1 frequency 25 MHz Jitter, one sigma1 Tabs1 CLK1 frequency 25 MHz Jitter, absolute1 1 T1s2 CLK1 frequency< 25 MHz Jitter, one sigma Tabs2 CLK1 frequency< 25 MHz Jitter, absolute1 Line-to-line jitter,1 absolute2 TLabs fi See allowable fi below: Input Frequency,1 IN or FBIN 12 fi 14 kHz 14 < fi 17 kHz fCLK1 17 < fi 30 kHz CLK1 Frequency1, 3, 4 30 < fi 35 kHz 35 < fi 1000 kHz Notes:
PARAMETER Input Clock Rise Time1 Input Clock Fall Time1 Output Rise Time1
MIN -- -- -- -- -- -- 40 -- -400 -- -- -- 12 44.0 30.0 25.0 15.0 10.0
TYP -- -- 0.6 1.6 1.0 0.9 47 120 250 -- -- 4 -- -- -- -- -- --
MAX 10 10 1.5 3.0 2.0 2.0 55 250 400 1 2 -- 1000 75 75 75 75 75
UNITS ns ns ns ns ns ns % ps ps % % ns kHz MHz MHz MHz MHz MHz
1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following these guidelines, the AV9173 will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot variation.
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AV9173-01
8-Pin DIP PACKAGE
8-Pin SOIC PACKAGE
Ordering Information
AV9173-01CN08 - or - AV9173-01CS08
Example:
XXX XXXX - PPP M X#W
Lead Count & Package Width Lead Count = 1, 2 or 3 digits W = 0.3" SOIC or 0.6" DIP; None = Standard Width Package Type N = DIP (Plastic) S = SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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